instruction scheduling


instruction scheduling

The compiler phase that orders instructions on apipelined, superscalar, or VLIW architecture so as tomaximise the number of function units operating in paralleland to minimise the time they spend waiting for each other.

Examples are filling a delay slot; interspersingfloating-point instructions with integer instructions tokeep both units operating; making adjacent instructionsindependent, e.g. one which writes a register and another whichreads from it; separating memory writes to avoid filling thewrite buffer.

Norman P. Jouppi and David W. Wall, "Available Instruction-Level Parallelism for Superscalar and Superpipelined Processors",Proceedings of the Third International Conference onArchitectural Support for Programming Languages and OperatingSystems, pp. 272--282, 1989.

[The SPARC Architecture Manual, v8, ISBN 0-13-825001-4]