level-sensitive scan design

(circuit design) (LSSD) A kind of scan design which usesseparate system and scan clocks to distinguish between normaland test mode. Latches are used in pairs, each has a normaldata input, data output and clock for system operation. Fortest operation, the two latches form a master/slave pair withone scan input, one scan output and non-overlapping scanclocks A and B which are held low during system operation butcause the scan data to be latched when pulsed high duringscan.

____| |Sin ----|S |A ------|> || Q|---+--------------- Q1D1 -----|D | |CLK1 ---|> | ||____| | ____| | |+---|S |B -------------------|> || Q|------ Q2 / SOutD2 ------------------|D |CLK2 ----------------|> ||____|

In a single latch LSSD configuration, the second latch is usedonly for scan operation. Allowing it to be use as a secondsystem latch reduces the silicon overhead.

单词	level-sensitive scan design
释义	level-sensitive scan design level-sensitive scan design (circuit design) (LSSD) A kind of scan design which usesseparate system and scan clocks to distinguish between normaland test mode. Latches are used in pairs, each has a normaldata input, data output and clock for system operation. Fortest operation, the two latches form a master/slave pair withone scan input, one scan output and non-overlapping scanclocks A and B which are held low during system operation butcause the scan data to be latched when pulsed high duringscan. ____\| \|Sin ----\|S \|A ------\|> \|\| Q\|---+--------------- Q1D1 -----\|D \| \|CLK1 ---\|> \| \|\|____\| \| ____\| \| \|+---\|S \|B -------------------\|> \|\| Q\|------ Q2 / SOutD2 ------------------\|D \|CLK2 ----------------\|> \|\|____\| In a single latch LSSD configuration, the second latch is usedonly for scan operation. Allowing it to be use as a secondsystem latch reduces the silicon overhead.
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