Nibble Mode DRAM

Nibble Mode DRAM

(storage)A standard DRAM where four successive bits canbe clocked out of the single data line by successive pulses onthe CAS\\ line while RAS\\ is active. A column address is onlyrequired for the first bit.

This mode is now unfashionable but can be found on some older64 kilobit and 256 kilobit chips.