soft core

softcore

1. Depicting erotic sexual content or activity without containing explicit or graphic images or descriptions, especially of penetration or genitalia (i.e. "hardcore"). The magazine has been accused of being little more than softcore pornography. It's being described as an art film depicting the true nature of an adult relationship, but it's just softcore porn, if you ask me.2. Not particularly extreme in one's dedication to something. I still love playing video games, but I'm just a softcore gamer these days. We're all pretty softcore fans of football. We love watching it when it's on, but we don't follow it religiously or anything.

soft core

1. mod. referring to a mild type of pornography. Now even the soft core stuff is getting harder to find at newsstands. 2. n. mild pornography. They keep some soft core under the counter. See also: core, soft

soft core

A block of digital logic that is designed to be implemented in an ASIC or FPGA chip. A soft core is typically delivered in RTL, which is a hardware description language that defines logic at a higher level than a "hard core," which is at the gate level. A chip design may comprise one or more soft cores combined with one or more hard cores along with other blocks of user-defined logic. Occasionally, soft cores are delivered as gate-level netlists or schematics rather than RTL.

Soft Cores in ASICs
For ASIC chips, the RTL soft core and other RTL associated with the design are synthesized into a gate-level netlist. Based on the netlist, the logic gates are placed and routed and then turned into photomasks to make the chip. The ultimate realization of the soft core is hardwired logic gates formed of transistors and their interconnections.

Soft Cores in FPGAs
With FPGAs, the resulting netlist is used to generate a configuration file that will be used to program the lookup tables and configurable logic blocks inside the device. See core, hard core, netlist, ASIC and FPGA.

How Soft Cores Fit In

Soft cores delivered in RTL are the first stage of circuit development. This chart illustrates an ASIC chip. With FPGAs, the microprocessor core and other IP blocks are already in place. Consequently, instead of a gate-level netlist, a lookup table/configurable logic block (LUT/CLB) netlist is created, and the final output for FPGAs is a configuration file rather than GDSII files.