Advanced RISC Machine

(processor)(ARM, Originally Acorn RISC Machine). A seriesof low-cost, power-efficient 32-bit RISC microprocessorsfor embedded control, computing, digital signal processing,games, consumer multimedia and portable applications. Itwas the first commercial RISC microprocessor (or was the MIPS R2000?) and was licensed for production by Asahi Kasei Microsystems, Cirrus Logic, GEC Plessey Semiconductors,Samsung, Sharp, Texas Instruments and VLSI Technology.

The ARM has a small and highly orthogonal instruction set,as do most RISC processors. Every instruction includes afour-bit code which specifies a condition (of the processor status register) which must be satisfied for the instructionto be executed. Unconditional execution is specified with acondition "true".

Instructions are split into load and store which access memoryand arithmetic and logic instructions which work onregisters (two source and one destination).

The ARM has 27 registers of which 16 are accessible in anyparticular processor mode. R15 combines the program counterand processor status byte, the other registers are generalpurpose except that R14 holds the return address after asubroutine call and R13 is conventionally used as a stack pointer. There are four processor modes: user, interrupt(with a private copy of R13 and R14), fast interrupt (privatecopies of R8 to R14) and supervisor (private copies of R13and R14). The ALU includes a 32-bit barrel-shifterallowing, e.g., a single-cycle shift and add.

The first ARM processor, the ARM1 was a prototype which wasnever released. The ARM2 was originally called the Acorn RISCMachine. It was designed by Acorn Computers Ltd. and usedin the original Archimedes, their successor to the BBC Micro and BBC Master series which were based on theeight-bit 6502 microprocessor. It was clocked at 8 MHzgiving an average performance of 4 - 4.7 MIPS. Developmentof the ARM family was then continued by a new company,Advanced RISC Machines Ltd.

The ARM3 added a fully-associative on-chip cache andsome support for multiprocessing. This was followed by theARM600 chip which was an ARM6 processor core with a4-kilobyte 64-way set-associative cache, an MMU based onthe MEMC2 chip, a write buffer (8 words?) and acoprocessor interface.

The ARM7 processor core uses half the power of the ARM6and takes around half the die size. In a full processordesign (ARM700 chip) it should provide 50% to 100% moreperformance.

In July 1994 VLSI Technology, Inc. released the ARM710processor chip.

Thumb is an implementation with reduced code sizerequirements, intended for embedded applications.

An ARM800 chip is also planned.

AT&T, IBM, Panasonic, Apple Coputer, Matsushita andSanyo either rely on, or manufacture, ARM 32-bit processorchips.

Usenet newsgroup: news:comp.sys.arm.

单词	advanced risc machine
释义	Advanced RISC Machine Advanced RISC Machine (processor)(ARM, Originally Acorn RISC Machine). A seriesof low-cost, power-efficient 32-bit RISC microprocessorsfor embedded control, computing, digital signal processing,games, consumer multimedia and portable applications. Itwas the first commercial RISC microprocessor (or was the MIPS R2000?) and was licensed for production by Asahi Kasei Microsystems, Cirrus Logic, GEC Plessey Semiconductors,Samsung, Sharp, Texas Instruments and VLSI Technology. The ARM has a small and highly orthogonal instruction set,as do most RISC processors. Every instruction includes afour-bit code which specifies a condition (of the processor status register) which must be satisfied for the instructionto be executed. Unconditional execution is specified with acondition "true". Instructions are split into load and store which access memoryand arithmetic and logic instructions which work onregisters (two source and one destination). The ARM has 27 registers of which 16 are accessible in anyparticular processor mode. R15 combines the program counterand processor status byte, the other registers are generalpurpose except that R14 holds the return address after asubroutine call and R13 is conventionally used as a stack pointer. There are four processor modes: user, interrupt(with a private copy of R13 and R14), fast interrupt (privatecopies of R8 to R14) and supervisor (private copies of R13and R14). The ALU includes a 32-bit barrel-shifterallowing, e.g., a single-cycle shift and add. The first ARM processor, the ARM1 was a prototype which wasnever released. The ARM2 was originally called the Acorn RISCMachine. It was designed by Acorn Computers Ltd. and usedin the original Archimedes, their successor to the BBC Micro and BBC Master series which were based on theeight-bit 6502 microprocessor. It was clocked at 8 MHzgiving an average performance of 4 - 4.7 MIPS. Developmentof the ARM family was then continued by a new company,Advanced RISC Machines Ltd. The ARM3 added a fully-associative on-chip cache andsome support for multiprocessing. This was followed by theARM600 chip which was an ARM6 processor core with a4-kilobyte 64-way set-associative cache, an MMU based onthe MEMC2 chip, a write buffer (8 words?) and acoprocessor interface. The ARM7 processor core uses half the power of the ARM6and takes around half the die size. In a full processordesign (ARM700 chip) it should provide 50% to 100% moreperformance. In July 1994 VLSI Technology, Inc. released the ARM710processor chip. Thumb is an implementation with reduced code sizerequirements, intended for embedded applications. An ARM800 chip is also planned. AT&T, IBM, Panasonic, Apple Coputer, Matsushita andSanyo either rely on, or manufacture, ARM 32-bit processorchips. Usenet newsgroup: news:comp.sys.arm. See ARM See ARM
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