释义 |
phase-locked loop
phase-locked loop[′fāz ¦läkt ′lüp] (electronics) A circuit that consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference-frequency generator; the output of the phase detector, after passing through a loop filter, is fed back to the voltage-controlled oscillator to keep it exactly in phase with the incoming or reference frequency. Abbreviated PLL. AcronymsSeePLL |