| 释义 |
pipeline break pipeline break (architecture)(Or "pipeline stall") The delay caused on aprocessor using pipelines when a transfer of control istaken. Normally when a control-transfer instruction (abranch, conditional branch, call or trap) is taken, anyfollowing instructions which have been loaded into theprocessor's pipeline must be discarded or "flushed" and newinstructions loaded from the branch destination. Thisintroduces a delay before the processor can resume execution.
"Delayed control-transfer" is a technique used to reducethis effect. |