Scalable Processor ARChitecture


Scalable Processor ARChitecture

(computer)(SPARC) An instruction set architecture designedby Sun Microsystems for their own use in 1985. Sun was amaker of 680x0-based Unix workstations. Researchversions of RISC processors had promised a major stepforward in speed but existing manufacturers were slow tointroduce a RISC type processor, so Sun went ahead anddeveloped its own, based on the University of California at Berkley's RISC I and RISC II 1980-2. In keeping withtheir open philosophy, they licenced it to other companies,rather than manufacture it themselves. The evolution andstandardisation of SPARC is now directed by the non-profitconsortium SPARC International, Inc.

SPARC was not the first RISC processor. The AMD 29000came before it, as did the MIPS R2000 (based on Stanford'sdesign) and Hewlett-Packard Precision Architecture CPU,among others. The SPARC design was radical at the time, evenomitting multiple cycle multiply and divide instructions (likea few others), while most RISC CPUs are more conventional.

SPARC implementations usually contain 128 or 144 registers,(CISC designs typically had 16 or less). At each time 32registers are available - 8 are global, the rest are allocatedin a "window" from a stack of registers. The window is moved16 registers down the stack during a function call, so thatthe upper and lower 8 registers are shared between functions,to pass and return values, and 8 are local. The window ismoved up on return, so registers are loaded or saved only atthe top or bottom of the register stack. This allowsfunctions to be called in as little as 1 cycle. Like someother RISC processors, reading global register zero alwaysreturns zero and writing it has no effect. SPARC ispipelined for performance, and like previous processors, adedicated condition code register holds comparison results.

SPARC is "scalable" mainly because the register stack can beexpanded (up to 512, or 32 windows), to reduce loads and savesbetween functions, or scaled down to reduce interrupt orcontext switch time, when the entire register set has to besaved. Function calls are usually much more frequent, so thelarge register set is usually a plus.

SPARC is not a chip, but a specification, and so there arevarious implementations of it. It has undergone revisions,and now has multiply and divide instructions. Most versionsare 32 bits, but there are designs for 64-bit andsuperscalar versions. SPARC was submitted to the IEEEsociety to be considered for the P1754 microprocessorstandard.

SPARC(R) is a registered trademark of SPARC International,Inc. in the United States and other countries.

[The SPARC Architecture Manual, v8, ISBN 0-13-825001-4].