Planar Process

planar process

[′plā·nər ‚prä·səs] (engineering) A silicon-transistor manufacturing process in which a fractional-micrometer-thick oxide layer is grown on a silicon substrate; a series of etching and diffusion steps is then used to produce the transistor inside the silicon substrate.

Planar Process

originally, the operations involved in the fabrication of semiconductor devices with p-n junctions that terminate in the same plane surface of a semiconductor wafer and are located beneath a layer of a protective dielectric coating. In the current, broader sense, planar process is the name for operations involved in the fabrication of practically any semiconductor devices and integrated circuits, including those in which the p-n junctions do not terminate in a single plane surface. The terms “planar process” and “planar device” were coined in 1959 when the American company Fairchild created the first planar silicon transistors.

The principal operations in the fabrication of the classical planar silicon transistor with n-p-n junctions are performed in the following sequence. A flat surface of a wafer of single-crystal silicon with n-type conductivity is lapped and then polished and carefully cleaned (Figure 1,a). A layer of silicon dioxide (SiO₂) ranging in thickness from a few tenths of a micron (μ) to 1.0–1.5μ is formed by thermal oxidation in dry or moist oxygen on this surface (Figure 1,b). The layer is then treated photolitho-graphically. In this process, a layer of a photoresist sensitive to ultraviolet radiation is applied to the oxidized silicon surface. The wafer with the dried photoresist layer is placed under a mask —a glass plate with a pattern that is transparent in certain places to ultraviolet radiation. After exposure to the radiation, the photoresist is polymerized (hardened) at the places below which the SÌO2 layer should be preserved. The photoresist is removed from the remainder of the wafer, the exposed SÌO2 layer is eliminated by etching, and then the remaining photoresist is removed (Figure 1,c). Boron (the acceptor impurity) is thereupon diffused into the areas where there is no oxide film in order to create in the material of the original wafer (the collector region) a base region with p-type conductivity. Since diffusion occurs simultaneously both perpendicular and parallel to the surface of the wafer—that is, under the edges of the oxide film—the boundaries of the p-n junction between the collector and base regions, which reach the surface of the wafer, are sealed by a SÌO2 layer (Figure 1,d). After, or simultaneously with, the boron diffusion, the surface of the wafer is subjected again to oxidation, and photolithographic treatment (Figure 1,e) is carried out once more in order to create an emitter region with n-type conductivity by diffusion of phosphorus (a donor impurity) into prescribed areas of the base region. In the process, the boundaries of the p-n junctions between the emitter and the base regions are also sealed by the SiO₂ layer (Figure 1,f). After, or simultaneously with, donor diffusion, a third oxidation is carried out, and a layer of pure SiO₂ or a phosphorus-silicate glass is formed over the emitter region. Then, the final photolithographic treatment is carried out and holes for contacts are etched in the oxide film over the emitter and base regions (Figure 1,g). The contacts are formed by applying a thin metal film, which is usually of aluminum (Figure l,h). Contact to the collector region is accomplished by metallizing the lower surface of the original wafer. The silicon wafer is cut into individual crystals, each of which has the transistor structure. Finally, each crystal is placed in a package, which is hermetically sealed.

Figure 1. Stages in the fabrication of a planar transistor: (a) original wafer, (b) after first oxidation, (c) after first photolithographic treatment, (d) after creation of the base region and second oxidation, (e) after second photolithographic treatment, (f) after creation of the emitter region and third oxidation, (g) after third photolithographic treatment, (h) after metallization; (1) original silicon with n-type conductivity, (2) masking film of silicon dioxide, (3) base region, (4) emitter region, (5) metal film (contacts)

As planar process technology developed, it incorporated a number of new processes. Not only SiO₂ but silicon nitride, silicon oxynitride, and other substances came to be used in the protective films. Pyrolysis, reactive sputtering of silicon (in an oxygen environment), and other processes are used to produce these films. Electron-beam treatment, or electron lithography, is used in addition to conventional optical photolithography for the selective removal of the protective dielectric film. Besides diffusion, ion implantation of donor and acceptor impurities is used to dope the silicon. A combination of the methods of planar process technology with the techniques of epitaxial growth has become widespread. This combination has led to the development of a broad class of diverse planar-epitaxial semiconductor devices. It has become possible to produce stable protective dielectric films not only on silicon but on other semiconductor materials as well. As a result, planar semiconductor devices based on germanium and on gallium arsenide have been developed. In addition to boron and phosphorus, other elements of groups III and V of Mendeleev’s periodic system of the elements are used as doping impurities in semiconductor devices.

The main advantage of planar process—and the reason for its spread in semiconductor electronics—is its use as a method of mass production of semiconductor devices. Such an approach increases labor productivity and the percentage of devices that are usable and improves the uniformity of product parameters. The use in planar process technology of such precision processes as photolithography, diffusion, and ion implantation has made it possible to specify with great exactness the dimensions and properties of the regions being doped and, consequently, to obtain parameters and combinations thereof that are unattainable by other methods for the fabrication of semiconductor devices. Protective dielectric films covering the p-n junctions emerging on the surface of the semiconductor material permit the creation of devices with stable characteristics that vary little with time. A number of special measures are also useful in this regard. Thus, the surface of the wafer is carefully cleaned prior to application of the protective film, and very pure raw materials are used in producing the protective films—for example, twice-distilled water, which does not come into contact with the external environment after the second distillation.

REFERENCE

Kremnievye planarnye tranzistory. Edited by la. A. Fedotov. Moscow, 1973.
Mazel’, E. Z., and F. P. Press. Planarnaia tekhnologiia kremnievykh priborov. Moscow, 1974.

E. Z. MAZEL’

单词	planar process
释义	planar process planar process n (Electronics) a method of producing diffused junctions in semiconductor devices. A pattern of holes is etched into an oxide layer formed on a silicon substrate, into which impurities are diffused through the holes Planar Process planar process [′plā·nər ‚prä·səs] (engineering) A silicon-transistor manufacturing process in which a fractional-micrometer-thick oxide layer is grown on a silicon substrate; a series of etching and diffusion steps is then used to produce the transistor inside the silicon substrate. Planar Process originally, the operations involved in the fabrication of semiconductor devices with p-n junctions that terminate in the same plane surface of a semiconductor wafer and are located beneath a layer of a protective dielectric coating. In the current, broader sense, planar process is the name for operations involved in the fabrication of practically any semiconductor devices and integrated circuits, including those in which the p-n junctions do not terminate in a single plane surface. The terms “planar process” and “planar device” were coined in 1959 when the American company Fairchild created the first planar silicon transistors. The principal operations in the fabrication of the classical planar silicon transistor with n-p-n junctions are performed in the following sequence. A flat surface of a wafer of single-crystal silicon with n-type conductivity is lapped and then polished and carefully cleaned (Figure 1,a). A layer of silicon dioxide (SiO₂) ranging in thickness from a few tenths of a micron (μ) to 1.0–1.5μ is formed by thermal oxidation in dry or moist oxygen on this surface (Figure 1,b). The layer is then treated photolitho-graphically. In this process, a layer of a photoresist sensitive to ultraviolet radiation is applied to the oxidized silicon surface. The wafer with the dried photoresist layer is placed under a mask —a glass plate with a pattern that is transparent in certain places to ultraviolet radiation. After exposure to the radiation, the photoresist is polymerized (hardened) at the places below which the SÌO2 layer should be preserved. The photoresist is removed from the remainder of the wafer, the exposed SÌO2 layer is eliminated by etching, and then the remaining photoresist is removed (Figure 1,c). Boron (the acceptor impurity) is thereupon diffused into the areas where there is no oxide film in order to create in the material of the original wafer (the collector region) a base region with p-type conductivity. Since diffusion occurs simultaneously both perpendicular and parallel to the surface of the wafer—that is, under the edges of the oxide film—the boundaries of the p-n junction between the collector and base regions, which reach the surface of the wafer, are sealed by a SÌO2 layer (Figure 1,d). After, or simultaneously with, the boron diffusion, the surface of the wafer is subjected again to oxidation, and photolithographic treatment (Figure 1,e) is carried out once more in order to create an emitter region with n-type conductivity by diffusion of phosphorus (a donor impurity) into prescribed areas of the base region. In the process, the boundaries of the p-n junctions between the emitter and the base regions are also sealed by the SiO₂ layer (Figure 1,f). After, or simultaneously with, donor diffusion, a third oxidation is carried out, and a layer of pure SiO₂ or a phosphorus-silicate glass is formed over the emitter region. Then, the final photolithographic treatment is carried out and holes for contacts are etched in the oxide film over the emitter and base regions (Figure 1,g). The contacts are formed by applying a thin metal film, which is usually of aluminum (Figure l,h). Contact to the collector region is accomplished by metallizing the lower surface of the original wafer. The silicon wafer is cut into individual crystals, each of which has the transistor structure. Finally, each crystal is placed in a package, which is hermetically sealed. Figure 1. Stages in the fabrication of a planar transistor: (a) original wafer, (b) after first oxidation, (c) after first photolithographic treatment, (d) after creation of the base region and second oxidation, (e) after second photolithographic treatment, (f) after creation of the emitter region and third oxidation, (g) after third photolithographic treatment, (h) after metallization; (1) original silicon with n-type conductivity, (2) masking film of silicon dioxide, (3) base region, (4) emitter region, (5) metal film (contacts) As planar process technology developed, it incorporated a number of new processes. Not only SiO₂ but silicon nitride, silicon oxynitride, and other substances came to be used in the protective films. Pyrolysis, reactive sputtering of silicon (in an oxygen environment), and other processes are used to produce these films. Electron-beam treatment, or electron lithography, is used in addition to conventional optical photolithography for the selective removal of the protective dielectric film. Besides diffusion, ion implantation of donor and acceptor impurities is used to dope the silicon. A combination of the methods of planar process technology with the techniques of epitaxial growth has become widespread. This combination has led to the development of a broad class of diverse planar-epitaxial semiconductor devices. It has become possible to produce stable protective dielectric films not only on silicon but on other semiconductor materials as well. As a result, planar semiconductor devices based on germanium and on gallium arsenide have been developed. In addition to boron and phosphorus, other elements of groups III and V of Mendeleev’s periodic system of the elements are used as doping impurities in semiconductor devices. The main advantage of planar process—and the reason for its spread in semiconductor electronics—is its use as a method of mass production of semiconductor devices. Such an approach increases labor productivity and the percentage of devices that are usable and improves the uniformity of product parameters. The use in planar process technology of such precision processes as photolithography, diffusion, and ion implantation has made it possible to specify with great exactness the dimensions and properties of the regions being doped and, consequently, to obtain parameters and combinations thereof that are unattainable by other methods for the fabrication of semiconductor devices. Protective dielectric films covering the p-n junctions emerging on the surface of the semiconductor material permit the creation of devices with stable characteristics that vary little with time. A number of special measures are also useful in this regard. Thus, the surface of the wafer is carefully cleaned prior to application of the protective film, and very pure raw materials are used in producing the protective films—for example, twice-distilled water, which does not come into contact with the external environment after the second distillation. REFERENCE Kremnievye planarnye tranzistory. Edited by la. A. Fedotov. Moscow, 1973. Mazel’, E. Z., and F. P. Press. Planarnaia tekhnologiia kremnievykh priborov. Moscow, 1974. E. Z. MAZEL’
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