cache coherency


cache coherency

(storage)(Or "cache consistency") /kash koh-heer'n-see/ Thesynchronisation of data in multiple caches such that readinga memory location via any cache will return the most recentdata written to that location via any (other) cache.

Some parallel processors do not cache accesses to shared memory to avoid the issue of cache coherency. If caches areused with shared memory then some system is required to detectwhen data in one processor's cache should be discarded orreplaced because another processor has updated that memorylocation. Several such schemes have been devised.

cache coherency

Managing a cache so that data are not lost or overwritten. For example, when data are updated in a cache but not yet transferred to the target memory or disk, the chance of corruption is greater. Accomplished by well-designed algorithms that keep track of every read and write event, cache coherency is even more critical in symmetric multiprocessing (SMP) where memory is shared by multiple processors. See cache and SMP.